Allwinner /D1H /UART[4] /DMA_REQ_EN

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Interpret as DMA_REQ_EN

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (disable)rx_req_enable 0 (disable)tx_req_enable 0 (disable)timeout_enable

timeout_enable=disable, rx_req_enable=disable, tx_req_enable=disable

Description

UART DMA Request Enable Register

Fields

rx_req_enable

DMA RX REQ Enable

0 (disable): undefined

1 (enable): undefined

tx_req_enable

DMA TX REQ Enable

0 (disable): undefined

1 (enable): undefined

timeout_enable

DMA Timeout Enable

0 (disable): undefined

1 (enable): undefined

Links

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